This application claims the priority benefit of Taiwan application serial no. 89107440, filed Apr. 20, 2000.
1. Field of Invention
The present invention relates to a method of fabricating integrated circuits. More particularly, the present invention relates to a method of fabricating a dual metal gate.
2. Description of Related Art
In the present semiconductor manufacture processes, the integration required for integrated circuits is higher and the sizes of field effect transistors (FET) are smaller. When the size of the field effect transistor is less than 0.1 micron, the thickness of the gate oxide layer is less than about 20 Angstroms, that is, about six to seven layers of silicon oxide in a gate silicon oxide layer. Because the gate silicon oxide layer is pretty thin, electrons can easily diffuse through the gate silicon oxide layer and cause current leakage; furthermore, dopants might penetrate the gate silicon oxide layer through the defects and cause problems in electrical properties.
The thickness of the gate silicon oxide layer limits the size of the field effect transistor. In order to solve the problems caused by the gate silicon oxide layer, many dielectric materials with high dielectric constants are developed. These dielectric materials include: Ta2O5, Pb(Zr, Ti)O3 (PZT) and (Ba, Sr)TiO3 (BST), with dielectric constants of about 20-25 for Ta2O5, about 20-60 for BST and about 600-1000 for PZT.
However, a dielectric layer with a high dielectric constant cannot remain the original high dielectric constant, because a native oxide layer that has a lower dielectric constant is formed between the silicon substrate and the dielectric layer. This further influences the electrical performance of the minute transistor formed thereon.
As the thickness of the gate oxide layer decreases, poly depletion becomes more severe. Presently, metal gates replace polysilicon gates to prevent poly depletion and to reduce parasitic resistance. Moreover, the gate oxide layer in the peripheral region must be thicker than the gate oxide layer in the cell region, in order to increase breakdown voltage for outside circuit connections. In order to use dielectric materials with high dielectric constants for gate oxide layers in the metal gates, many difficulties must be overcome to achieve different thickness requirements for gate oxide layers in the cell region and the peripheral region and to increase the effective thickness of gate oxide layers for the high-integration IC manufacture process.
The invention provides a method of fabricating a dual metal gate. A substrate containing a cell region and a peripheral region is provided and a first dummy gate electrode and a second dummy gate electrode are formed on the substrate, respectively, in the cell region and in the peripheral region. Below the sidewalls of the first dummy gate electrode and the second dummy gate electrode, source/drains are formed in the substrate. A patterned first dielectric layer is formed above the substrate, and the layer exposes the surfaces of the first dummy gate electrode and the second dummy gate electrode. The first dummy gate electrode and the second dummy gate electrode are then removed to expose the substrate and an oxide layer is formed on the exposed substrate in the peripheral region. A remote plasma nitridation (RPN) step is performed to nitridate the surface of the exposed substrate in the cell region and to nitridate the oxide layer into a material layer in the peripheral region. A conformal second dielectric layer is formed above the substrate. A conducting layer is formed on the second dielectric layer and fills up trenches that are formed by removing the first dummy gate electrode and the second dummy gate electrode. A part of the second dielectric layer and a part of the conducting layer are removed until the surface of the first dielectric layer is exposed and a dual metal gate is completed thereon.
As embodied and broadly described herein, the RPN step is performed in an environment full of ammonia plasma or nitrogen plasma, at a temperature of about 500-800 degrees Centigrade, with a pressure less than 30 Torr, a plasma operation power of about 1000-5000 Watts and for a duration of about 30-90 seconds. Furthermore, metal silicides are formed on source/drains.
In this invention, a nitridation step is performed to nitridate the surfaces of the substrate and the surface of the oxide layer that are exposed by the trenches; therefore, the gate dielectric layer that is subsequently formed can maintain a higher dielectric constant. Moreover, gate dielectric layers of different thicknesses are formed respectively in the cell region and in the peripheral region (the effective thickness of the gate dielectric layer in the cell region is the sum of the thicknesses of the dielectric layer and the nitride layer, while the effective thickness of the gate dielectric layer in the peripheral region is the sum of the thicknesses of the dielectric layer and the material layer). Thus, this satisfies the requirement for a higher breakdown voltage in the peripheral region.
In this invention, metal gate layers are formed after metal silicide layers are formed on the source/drains; hence, the thermal budget of the manufacture process is reduced. The manufacture process of this invention is compatible with the prior art manufacture process for the gate dielectric layer; therefore, the manufacture processes can easily be integrated. In this invention, metal gate layers are formed after the source/drains are formed; therefore, the heat diffusion in the thermal process for forming source/drains does not result in contamination in the metal gate layers.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.